hm_fa_da
Full Member level 5
fpga delay
Hello all ,
is this a 50 ns delay in fpga ?:
clock := not clock after 50 ns ;
?
what range could be used for time ? is it dependent on device oscilator ? how long can it be maximum and minimum ? and how is it done in gates ??? i mean how a delay is done in fpga or cpld gates .... ?
Thanks & Best Regards
Hello all ,
is this a 50 ns delay in fpga ?:
clock := not clock after 50 ns ;
?
what range could be used for time ? is it dependent on device oscilator ? how long can it be maximum and minimum ? and how is it done in gates ??? i mean how a delay is done in fpga or cpld gates .... ?
Thanks & Best Regards