how to generate delay in fpga ?

[hm_fa_da]

fpga delay

Hello all ,

is this a 50 ns delay in fpga ?:
clock := not clock after 50 ns ;

?

what range could be used for time ? is it dependent on device oscilator ? how long can it be maximum and minimum ? and how is it done in gates ??? i mean how a delay is done in fpga or cpld gates .... ?

Thanks & Best Regards

 

[rakesh_aadhimoolam]

delay in fpga

Better go through this link.........



all the best......

 

[gliss]

delay fpga

Maybe you can use a ring oscillator.
Usually FPGAs have clock generators or PLLs has hard macros. Check the FPGA datasheet

 

[salma ali bakr]

using delay in fpga

The "After" keyword used for delays is ignored by the synthesis tool, because the tool knows that it's not synthesizable at this point in time.
It just mostly gives designers the ability to add delays into the RTL for modeling while still allowing the synthesizer to build circuit logic

 

[echo47]

implementing delay in fpga

Yes, modern FPGA synthesis tools generally ignore HDL delay values.

It is usually possible to build a crude time delay into an FPGA by using vendor-specific techniques (such as a chain of carefully-placed gates with optimization disabled), but the accuracy would be difficult to control, and 50ns is a long time in a modern fast FPGA. Such designs are generally not recommended. Instead, try to design your project using synchronous techniques. For example, you could generate a 50ns delay by feeding your signal through a 5-tap shift register clocked at 100MHz.

 

[hm_fa_da]

making delay with fpga

Dear all ,

Thanks for your replies ,

i am new to VHDL programming , i wanted to make a digital counter for example with my cpld - fpga board , one seven segment is connected to the MAX 7000 s CPLD , and the oscillator is 20 MHz , i wrote this program :

library ieee;
use ieee.std_logic_1164.all;

entity test_uni2 is
port (
s1 : out std_logic_vector ( 7 downto 0 ):= "00000011";
clk : in std_logic );
end test_uni2;

architecture counter of test_uni2 is
signal counter : integer range 0 to 20000005 := 0;
signal counter2 : integer range 0 to 15 := 0;
begin
process ( clk )
begin
if ( clk'event and clk = '1' ) then
counter <= counter+1 ;
if ( counter=20000000 ) then
counter <= 0;
counter2 <= counter2 + 1;
case counter2 is
when 0 => s1<= "00000011";
when 1 => s1<= "10011111";
when 2 => s1<= "00100101";
when 3 => s1<= "00001101";
when 4 => s1<= "10011001";
when 5 => s1<= "01001001";
when 6 => s1<= "01000001";
when 7 => s1<= "00011111";
when 8 => s1<= "00000001";
when 9 => s1<= "00001001";
counter2<= 0 ;
when others => counter2<= 0 ;
end case;
end if;
end if;
end process ;
end;

i haven't tested it in my board yet , but it works in Quartus simulator as i want ...,
but the problem is that in report of compilation , it says 51 of 128 macrocells are used for this program and i think it is too large for this ....
i used a counter to count 20,000,000 cycles of oscillator which is 20 MHz to make 1 second delay ...

What would you do if you were in my shoes ?!

 

[echo47]

fpga how to delay signal

I don't have Altera tools, but I'll try some guesses.

Your design doesn't fill up the device, so maybe your synthesizer didn't bother optimizing for smallest size.

Maybe you synthesizer is set to optimize for fastest speed instead of smallest size. Look for a switch.

Your design has 21 counter bits plus four counter2 bits, plus eight s1 encoder output bits. That explains 33 macrocells. Perhaps your synthesizer needed two macrocells to get enough product terms for the longer equations. Try implementing each section separately to see how many macrocells each section consumes.

 

[hm_fa_da]

how to provide delay in fpga

Thanks for your reply ,

i changed the optimazation from speed to area , now it uses 38 Macrocells, it is 30 % of cpld density .
however did i use a true way to make 1 second delay ? is there another way with fewer needed macrocells ... ?


Thanks & Best Regards.