making delay with fpga
Dear all ,
Thanks for your replies ,
i am new to VHDL programming , i wanted to make a digital counter for example with my cpld - fpga board , one seven segment is connected to the MAX 7000 s CPLD , and the oscillator is 20 MHz , i wrote this program :
library ieee;
use ieee.std_logic_1164.all;
entity test_uni2 is
port (
s1 : out std_logic_vector ( 7 downto 0 ):= "00000011";
clk : in std_logic );
end test_uni2;
architecture counter of test_uni2 is
signal counter : integer range 0 to 20000005 := 0;
signal counter2 : integer range 0 to 15 := 0;
begin
process ( clk )
begin
if ( clk'event and clk = '1' ) then
counter <= counter+1 ;
if ( counter=20000000 ) then
counter <= 0;
counter2 <= counter2 + 1;
case counter2 is
when 0 => s1<= "00000011";
when 1 => s1<= "10011111";
when 2 => s1<= "00100101";
when 3 => s1<= "00001101";
when 4 => s1<= "10011001";
when 5 => s1<= "01001001";
when 6 => s1<= "01000001";
when 7 => s1<= "00011111";
when 8 => s1<= "00000001";
when 9 => s1<= "00001001";
counter2<= 0 ;
when others => counter2<= 0 ;
end case;
end if;
end if;
end process ;
end;
i haven't tested it in my board yet , but it works in Quartus simulator as i want ...,
but the problem is that in report of compilation , it says 51 of 128 macrocells are used for this program and i think it is too large for this ....
i used a counter to count 20,000,000 cycles of oscillator which is 20 MHz to make 1 second delay ...
What would you do if you were in my shoes ?!