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No critical path is not between two registers in the module but it is when the timing is not met between an input nd output of a particular module. Please do confirm it. It is with respect to the clock when it violates timing(setup and hold time) and is offcourse the longest path
still blur .... i'm doing design for adder multiplier ... so when it become complex ... i donno which of my branch is the longest path .. i need to know coz wanna use logical effort to resize it for minimum delay
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i ' m using tanner v11.. any help to find it using this tool ?
In my experence , you must first decide which path is a FALSE path , the synthesis and TA tools just do things you told to . If any false path was not specified , tools will spend much more time to optimize or analysis the false path and leave the REAL critical path aside . AFter you told tools where is the false path , tools will do very well in critical path optimization .
It is the longest path between two flops. We calculate the frequency of operation by measing the delay between two flops. So the longest delay between two flops in a circuits is the critical path as it supports the Setup time for the flops