how to explain this sum behavior in verilog ?

[zhangljz]

Hello everyone,

I have a question about the sum operation in verilog in modelsim. Here is the code:

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Code Verilog - [expand]
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reg  sign;
  reg [1:0] delta;
  wire [1:0] sum_1, sum_2;
  wire [1:0] sign_x;
  
  initial begin
    sign =0;
    delta = 1;
  end
  
  assign sum_1 = delta + sign?3:0;
  
  assign sign_x = sign?3:0;
  assign sum_2 = delta + sign_x;

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The simulation shows sum_1 is 3, sum_2 is 1 which is what we expect.

I can not figure out why they have different behavior

Somebody can help ?

Thank you

 

[dave_59]

See Table 11-2—Operator precedence and associativity in the IEEE 1800-2012 LRM

 

[zhangljz]

Hi dave_59,

Thank you. I see why

It should be:
assign sum_1 = delta + (sign?3:0);

 

[ads-ee]

As a general rule I use parenthesis to enforce the correct precedence, regardless if it may be redundant. Saves you from having to debug gotchas like you observed.

e.g. if ( ((a == b) && (c == d)) || f )
instead of: if ( a==b && c==d || f )