Ridamir
Newbie level 3
Hello world !
After all, i want to mention that it's my first post in this forum and i'm glad to be a part of EDABOARD network.
In testbench, I have an issue with a procedure that I want to monitor its input parameter which is a signal, this signal may contains a number of my internal inputs AND/OR outputs of a module/s or top level design entity. Now the problem is how can I read continually this signal which may dynamically changes.
An alternative that I am using now is mapping this inputs/outputs to a signal of data_record_type :
But which this solution, I am limited with number of inputs/outputs mapped which make my procedure not useful for all, (e.g. if i have 69 inputs and 9 outputs which I need to monitor a combine of them in each step).
I read about access type in vhdl, but as i have seen it's juts for variables, and i am using signal and 'last_event attribute which make impossible for me to jump to variables. and the entry parameter is a signal.
Thanks for all.:-o
After all, i want to mention that it's my first post in this forum and i'm glad to be a part of EDABOARD network.
In testbench, I have an issue with a procedure that I want to monitor its input parameter which is a signal, this signal may contains a number of my internal inputs AND/OR outputs of a module/s or top level design entity. Now the problem is how can I read continually this signal which may dynamically changes.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 TYPE data_record IS ARRAY (natural range <>) OF STD_LOGIC; TYPE data_name_record IS ARRAY(natural range <>) OF STRING(1 TO 32); PROCEDURE MONITORING_VALUE( N : IN POSITIVE; SIGNAL INPUTS_OUTPUT : IN data_record ; EXPECTED_VALUE : IN data_record ; INPUTS_OUTPUT_NAME : IN data_name_record; MONITORING_TIME : IN TIME );
An alternative that I am using now is mapping this inputs/outputs to a signal of data_record_type :
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 SIGNAL INPUTS_ENTRED :data_record(0 TO N-1) := ('0', '0', '0', '0'); --=========================================================================== -- MAPPING: --=========================================================================== INPUTS_ENTRED(0) <= input1; INPUTS_ENTRED(1) <= input2 ; INPUTS_ENTRED(2) <= input3; INPUTS_ENTRED(3) <= output1;
But which this solution, I am limited with number of inputs/outputs mapped which make my procedure not useful for all, (e.g. if i have 69 inputs and 9 outputs which I need to monitor a combine of them in each step).
I read about access type in vhdl, but as i have seen it's juts for variables, and i am using signal and 'last_event attribute which make impossible for me to jump to variables. and the entry parameter is a signal.
Thanks for all.:-o