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how to do post simulation with ncverilog?

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ee_joe

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Hi all,
I want do post simulation with NCVERILOG.
What I have are *.v, *.lib, *.db and *.dspf, here the dspf file is RC parasitics extacted from layout, *.v is gate level netlist.
How to do the post simulation with back annotated dspf file and lib file?
thanks all!
 

ljxpjpjljx

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do you have SDF file ?'s more convinent for NCVERILOG to read and do post simulation.
 

asicganesh

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You need SDF + Synthesised netlist

I hope you have the synthesised netlist.

Normally in DC you can generate sdf using write_sdf command.. Mostly a similar instruction should be in RC also.. cross check..
 

ee_joe

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how does ncverilog work after read SDF file during simulation?
 

bossbebes

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Hi,

I would like to know what means SCOPE in the SDF file ?

Thxs a lot
 

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