[SOLVED] How to do copper pour with cadence virtuoso?

[bellona]

Hi, this is trivial in PCB design, but i don't know how to do this with RFIC design in cadence virtuoso, and google didn't return any useful results.
I think Copper pour is quite useful for maintaing a CPW enviorment for transmission lines and it will also help meeting CMP metal density requirements.
Thanks in advance

 

[erikl]

Depends on what you understand for copper pour: You can use the same method as on PCB: Use parallel wires on the same level, and additionally bottom & top lines covering the parallel wires and connect them by vias as close as possible - if you don't mind the additional capacitance.

 

[bellona]

Thanks for the reply, erikl. As to fringing capacitance, I figured out that won't hurt me much - In the process i'm using, when a signal line runs parallel with a ground plane with a separation of 10um between them, the fringing capacitance will be about 1fF per 20um of line run.
I've seen some RFIC layout with ground planes configurations just like what people usually do in PCB layout using copper pour, and i think this CPW-like environment is a nice way for controlling the current return path and reducing cross-talks between circuit blocks, besides the added benefits of low inductance power planes.
So i'm wondering if there is a simple way to do copper pour in IC layout tools like cadence virtuoso, without adding those metal mesh manually?

 

[erikl]

... i'm wondering if there is a simple way to do copper pour in IC layout tools like cadence virtuoso, without adding those metal mesh manually?

I don't know of any PDK which offers automatic shielding -- I've always done it manually, where necessary. But of course it could be automated via a SKILL routine, similar to, e.g., automatic creation of guard rings.

 

[bellona]

Thanks, erikel. I'm experimenting with Cadence's Routing IDE embeded in Virtuoso Layout GXL now. This router has the capability to do copper pour , though it's called power and ground stripes in the router.