Verilog Pro Question
Well this question may seem very stupid to most of you, but I am just a beginner trying to learn on my won.
When I run this program in verilog pro or Xilinx, I dont see any output.
How to display output without having toi write a testbench. I copied the program from a book, So I assume there are no errors. Also can someone suggest a free simulator for windows.
thanks all
module test;
integer i,j;
initial repeat(5)
begin
#1 j=0;
while (j<=10)
begin
j=j+1;
for (i=0;i<j;i=i+1) $write ("b");
$display ("*");
end
#1 while (j>=0)
begin
for(i=0;i<j;i=i+1) $write ("c");
$display ("*");
j=j-1;
end
end
initial #12 $stop;
endmodule