How to display output in Verilog Pro ?

[fidjouss100]

Verilog Pro Question

Well this question may seem very stupid to most of you, but I am just a beginner trying to learn on my won.

When I run this program in verilog pro or Xilinx, I dont see any output.
How to display output without having toi write a testbench. I copied the program from a book, So I assume there are no errors. Also can someone suggest a free simulator for windows.
thanks all


module test;
integer i,j;
initial repeat(5)
begin
#1 j=0;
while (j<=10)
begin
j=j+1;
for (i=0;i<j;i=i+1) $write ("b");
$display ("*");
end
#1 while (j>=0)
begin
for(i=0;i<j;i=i+1) $write ("c");
$display ("*");
j=j-1;
end
end
initial #12 $stop;
endmodule

 

[selingeorge]

Re: Verilog Pro Question

Try practicing to write testbench along with the program. You can use "silos" simulator for IEEE 1364-2001 compliant verilog simulation. It is freely available with Book CD "Verilog HDL, A Guide to Digital Design and Synthesis", Authored by Samir Palnitkar.

Best Regards.

 

[fidjouss100]

Re: Verilog Pro Question

I dont think you have to write a testbench for such a program. right?

 

[thedesolatesoul]

Re: Verilog Pro Question

No testbench is needed for such a program since there are no input/outputs to the module to stimulate.
ModelSIM is usually used for simulation but its a bit complex.
I'd recommend Veriogger Pro from Synapticad (Evaluation version) since I started from it myself.
Best of Luck.

 

[echo47]

Re: Verilog Pro Question

If you have ModelSim but haven't tried it, you can run it from the command line like this:

vlib work         create working library directory
vlog test.v       compile your code
vsim -c test      launch the simulator in command-line mode
run               run the simulation (it will display the results)
exit              exit the simulator

If you omit the -c it will run in GUI mode.

A light version of ModelSim comes with the free Xilinx WebPACK.