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How to disable some clock gating check in SDC ?

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lx1019

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Hi all ,

When doing STA using PT. It reports some unnecessary violations of the **clock_gating_default** group.

From the PT manual, I find out by using the PT command "set_disable_clock_gating_check cells" could disable these unnecessary checking.

But how to disable them in SDC file? So that the backend tool don't care these unnecessary checking.

Take a AND gate as a clock gating cell for example. When I use "set_false_path -to [get_cells AND]" ,

PT gives warning that the AND cell is not a valid endpoint.

Thanks!
 
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chiplogic

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Hi,
clock gating checks are not unnecessary checks...
Your design should not have any clock gating violations.
you can disable clock gating checks using set_disable_timing also...
You can ask PT to dump only REG2REG/REG2OUT/IN2REG paths using -group option in report_timing...
Hi all ,

When doing STA using PT. It reports some unnecessary violations of the **clock_gating_default** group.

From the PT manual, I find out by using the PT command "set_disable_clock_gating_check cells" could disable these unnecessary checking.

But how to disable them in SDC file? So that the backend tool don't care these unnecessary checking.

Take a AND gate as a clock gating cell for example. When I use "set_false_path -to [get_cells AND]" ,

PT gives warning that the AND cell is not a valid endpoint.

Thanks!
 

lx1019

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Yes, the clock gating is not unnecessary.
But some cells that PT takes as a clock gating cell is not the real clock gating cells we want.
For example, a MUX that select several clocks to output for debug purpose.

I don't want to disable all the clock gating checks, but only the unnecessary.
Now my solution is using "set_false_path -through clk_gating_cell" .
Is there any other better solution?
 

chiplogic

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why can't you try "set_disable_clock_gating_check <<cell name/pinname>>
 

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