how to design io pads

[siva_7517]

Hi,

I have just strated working on io pad design, but currently dont have a good resource to design io pad. I am trying to develop the pads by using verilog coding. Can anyone give some example on how to develop .io file. Software that i am using are PKS and encounter.
Thanx

Siva

 

[leeenghan]

Hi Siva,

I am confused.

I thought IO pad design is analog, and should be designed in transistor level, and layout is custom crafted.

If you are talking about logic squeeze into the pad then it is digital design, and has llittle to do with IO pad.

I am interested to learn what is you job scope.

Regards,
Eng Han
www.eda-utilities.com

 

[dwilliam]

I am also confused?!...

How can we design the ESD protection devices, multiple guard and power-rings on verilog?
I find it difficult, even with VerilogA, is not appropriate to use for simulation of IO cells. And we can not forget that the protection devices have exotic behaviour (like snap-back) on a ESD discharge, witch is difficult to model on most electric simulators...

Can you especify more?

 

[selvaraja]

confusing statement please be clear what u askin. thank you

 

[siva_7517]

Hi,

Sorry for the confusion. Actually, I have no idea on how to create an IO pad in my digital IC design. Can I design using PKS cadence? Thanx

Siva