I have just strated working on io pad design, but currently dont have a good resource to design io pad. I am trying to develop the pads by using verilog coding. Can anyone give some example on how to develop .io file. Software that i am using are PKS and encounter.
Thanx
How can we design the ESD protection devices, multiple guard and power-rings on verilog?
I find it difficult, even with VerilogA, is not appropriate to use for simulation of IO cells. And we can not forget that the protection devices have exotic behaviour (like snap-back) on a ESD discharge, witch is difficult to model on most electric simulators...