thanks for all reply.
my application is
cpu write and read data of configuration register at some clock frequency, but hardware engine use these configuration data as input signals.
1 double clock for control signals, these control signals including write and read enable ,not including address, data bus?
2 memory scheme is good choice,but my write signal has address bus,but read register not need address, I just want to connect these registers data to my hardware as input signals.
3 fifo scheme is not use for this case because it can not provide random access.