how to design asynchronous read and write register

[floatgrass]

hi, all
I want to different clock domain to read and write register file.How do I deal with the metastablility problem?

thanks!

 

[arnarendra]

I guess you can double clock the control signals used for read/write which will avoid the metastability problem.

 

[muralicrl]

Hi,

You can write and read from a memory with to avoid metastability condition as follows

write_clk <= CLK;
read_clk <= NOT write_clk;

 

[akshay.raoy]

use fifo for this purpose.

 

[floatgrass]

thanks for all reply.

my application is
cpu write and read data of configuration register at some clock frequency, but hardware engine use these configuration data as input signals.

1 double clock for control signals, these control signals including write and read enable ,not including address, data bus?

2 memory scheme is good choice,but my write signal has address bus,but read register not need address, I just want to connect these registers data to my hardware as input signals.

3 fifo scheme is not use for this case because it can not provide random access.

 

[WzWzWz]

Maybe handshake is better for your design, you write data with one clock and rise a flag to indicate the data is ready to read, the read signal read data with the synced flag. and vise versa.