How to design a low output noise voltage regulator?

[wylee]

output noise site:edaboard.com

Recently I designed a 3.3 to 1.8V 0.18um CMOS voltage regulator for one of my company's high speed (>2Gbps) project

I realized that the output voltage of the regulater fluctuated a lot due the switching noise in the circuit being decoupled back into the regulator itself.

I am trying to design the regulator hopefully without the need of external filtering cap.

Can anyone suggest me a good architecture on this?

Another question is about the power MOS at the output stage, normally a PMOS implementation is better or NMOS?

 

[electronrancher]

output noise voltage

that is a psrr problem. look at increasing the psrr of your error amp by cascoding mirrors at the top and bottom of your diff pair. you also need to increase length way beyond 0.18u. not sure what gds would be in your process, but start at 1um and work up. I think somewhere around 2um for pmos and 5um for nmos will be a good guess but you need to look at gds in your spice output to find out.

the big power device can use minimum length, but precision analog suffers badly (and will be unusable) at this small l and low Rout.

second. for the output stage you must use pmos. you want to convert from 3.3v to 1.8 - nmos could only give you shunt regulator, not a pass regulator without boosting gate drive above 3-4v due to the strong body effect from 1.8v output.