Delay!! Help!
Dear avimit,
I told above word because you was telling these types of circuit not allowded in digital design.and above circuit will work for sync reset removal when we are doing reset from other clock domain (I told these not related with question but related with that circuit features in multiple clock domain design). this type circuit is used in this paper also CummingsSNUG2002SJ_FIFO2.pdf.
Yes above type circuit will not work for if we have to delay the -ive of the incoming signal by jsut one clock cycle , for that purpose we required state machine design only ...
Regards