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hey i think this circuit could be easily designed using a divide by four counter...its pretty simple if you know state machine design...are you going to implement it in HDL or a in circuit using discrete components...
Its true that we will required mod 4 counter.
in addition to that,to delay negative edge by 2 clock cycles, we must exor the outputs Q0 and Q1.
Q0 exor Q1 will give you the reqd waveform.
If logic 1 comes, both the flipflops are set so the output comes out without any delay. When the logic goes to 0 the set is removed . So the logic zero is delayed by two clock cycles as it has to pass through two flipflop.
I guess you are not allowed to use this kind of circuitry in digital design, where you are affecting datapath by Async Set/resets. So I wont buy your idea/solution
These type of circuit is allowded when passing signal from one clock domain to another clock domain ,and above circuit will work like above problem and as well like synchronous reset removal..
1st flop can go into metastable but second flop will work like synchronizer.
jaseel_abdulla you can design your problem using state machine like this(assumption ositive edge shouldn't be delayed )
Present state Next State, op
i/p=0 i/p =1
A A,0 B,1
B C,1 B,1
C D,1 B,1
D A,0 B,1
After solving Kmap you will get these expression (q1=>MSB,q0=>LSB)
D0 = i/p + q1q0_bar
D1=i/p_bar( q1 exor q0)
O/p = i/p + (q1 exor q0)
With all respect, I would say that I dont agree with you on this occasion.
1.Where does clock domain corssing comes from? in this simple question
2.Say if we have to delay the -ive of the incoming signal by jsut one clock cycle then?
3. In normal digital design, these type of circuits are not recommended, if you feel 'allowed' it a bit strong here.
4. And I dont even understand where does 'sync reset removal' comes from in this simple problem.
I told above word because you was telling these types of circuit not allowded in digital design.and above circuit will work for sync reset removal when we are doing reset from other clock domain (I told these not related with question but related with that circuit features in multiple clock domain design). this type circuit is used in this paper also CummingsSNUG2002SJ_FIFO2.pdf.
Yes above type circuit will not work for if we have to delay the -ive of the incoming signal by jsut one clock cycle , for that purpose we required state machine design only ...
In that case, pls accept my apologies.. Yes, OK, these kind of circuts are accepted in special cases as pointed out by uditkumar1983. But I wont accept them in the context of this question.