Oct 31, 2007 #1 M manasiw2 Member level 1 Joined Oct 3, 2007 Messages 39 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,288 Activity points 1,476 Hi. I need to do following, output should follw input after two system clock cycles. Please suggest how to do it in VHDL. thanks in advance.
Hi. I need to do following, output should follw input after two system clock cycles. Please suggest how to do it in VHDL. thanks in advance.
Oct 31, 2007 #2 L laststep Member level 3 Joined Jan 24, 2007 Messages 66 Helped 7 Reputation 14 Reaction score 0 Trophy points 1,286 Location Malaysia Activity points 1,751 The easy way is just add 2 register by serial and sample the output of last register.
Nov 2, 2007 #3 M mukesh1981 Newbie level 5 Joined Feb 2, 2007 Messages 9 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 1,322 hi Just use double flopping nothing but two flip flops in serial, that output will be two clock cycles delayed with respect to input.
hi Just use double flopping nothing but two flip flops in serial, that output will be two clock cycles delayed with respect to input.
Nov 2, 2007 #4 M manasiw2 Member level 1 Joined Oct 3, 2007 Messages 39 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,288 Activity points 1,476 ya i got it....thanks all.