how to declare inout in behavioral modeling in Verilog HDL

[iyyappanbala]

Dear friends,

please help me to solve this problem,
How to swap number in behavioral modeling(non Blocking) Verilog Hdl,

module swap(a,b);
inout [3:0] a,b;
reg [3:0] a,b;
always@(a,b)
begin
b<=a;
a<=b;
end
endmodule

 

[ads-ee]

You can't. Better read your Verilog book again.

And don't use non-blocking in a non-posedge sensitive always block unless you like to have the potential for simulation synthesis mismatches (resulting in hardware that doesn't work correctly).

i.e. do this:

---

Code Verilog - [expand]
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always @ (posedge clk) begin
  non_blocking_assignment <= used_here;
end
 
always @ (used_here) begin
  blocking_assignment = used_here;
end

---

...and avoid this:

---

Code Verilog - [expand]
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always @ (posedge clk) begin
  blocking_assignment = dont_use_this;
end
 
always @ (dont_use_this) begin
  non_blocking_assignment <= dont_use_this;
end

---

If you want to swap (for simulation purposes only) then use blocking assignments like so:

---

Code Verilog - [expand]
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`timescale 1ns/1ns
module t;
 
reg [7:0] old_a, a, b;
initial begin
  a = 7;
  b = 3;
  $display ("Initial values:\n%t - a = %h, b = %h, old_a = %h", $time, a, b, old_a);
  #100;
  a = 5;
  b = 8;
  $display ("Initial values:\n%t - a = %h, b = %h, old_a = %h", $time, a, b, old_a);
  #100;
end
 
always @* begin
  old_a = a;
  a = b;
  b = old_a;
end
 
initial begin
  $monitor ("Swapped values:\n%t - a = %h, b = %h, old_a = %h", $time, a, b, old_a);
end
 
endmodule

---

Of course this is unrealistic behavior and is only for simulation purposes.