how to debug what is going inside fpga in real time

[s3034585]

chipscope_tutorial.pdf

hi guys
can any one please tell me how to debug what is going inside a fpga in realt time.
in my project i am using a pci core and some logic inside a fpga. the software interacts with the fpga thru pci port. so is it possible to debug inside fpga when it is interacting with the software thru pci port. i dont have a logic analyser so is there any other method to do it. i also want to debug the block ram which i am using..


it is really urgent pls help ..

thanks tama

 

[jayanth03]

If you are using a Xilinx FPGA.... then you can use ChipScope Logic Analyser for debugging...
**broken link removed**

 

[s3034585]

Hi Jayant
Thanks for your info. I went thruw that website. i could not understand wht does it mean by one needs to set trigger. how can i just monitor the internal buses while the fpga is interacting with software thru PCI.

thanks in advance
tama

 

[jayanth03]

Select the core type you wanna generate using ChipScope core generator...I did choose ILA... then this core along with your design goes into the FPGA using ChipScope core inserter... Then you can view the waveforms on the ChipScope logic analyser....
Select a input signal as trigger such that.. you get to watch other signals that are triggered just after an event on this signal... You might wanna select all the signals you want to view...

This Xilinx manual will help you how to do it...

https://www.xilinx.com/ise/verification/chipscope_pro_siotk_8_1i_ug213.pdf


Other helps:

**broken link removed**

**broken link removed**

 

[s3034585]

Select the core type you wanna generate using ChipScope core generator...I did choose ILA... then this core along with your design goes into the FPGA using ChipScope core inserter... Then you can view the waveforms on the ChipScope logic analyser....
Select a input signal as trigger such that.. you get to watch other signals that are triggered just after an event on this signal... You might wanna select all the signals you want to view...

This Xilinx manual will help you how to do it...

http://www.xilinx.com/ise/verification/chipscope_pro_siotk_8_1i_ug213.pdf


Other helps:

broken link removed

Hi Jayant
Thanks for your reply
i am still having a confusion about the communication with the fpga for debuging.
what i mean is that the software will interact with the fpga thru pci port and at the same time using chipscope with the help of jtag port we can monitor the waveforms also. but inorder to acess the fpga using jtag port we need to program the fpga using jtag port right using impact tool. But in my case the board has a smart media card to program it. so i generate the bit files only and then copy them to the smart media and restart the pc.

can you please explain this....

thanks in advance

tama

 

[ikru26]

for debugging inside the RTL we use Synplicity's RTL Debugger.thru this u can go to the nth level of your RTL source codee. go to their website and i think you can get evaluation version

 

[jayanth03]

You need to have the Jtag connected to the board at all times to debug...cuz the chipscope cummunicates through this cable... I am not aware of any other alternatives...
Does you board also have a Jtag interface??? I am assuming that your smart media card has enough space to accomdate even the chipscope core... If that is the case Xilinx XST will insert the core into u r design and generate a .bit file for u that you can load into u r smart media card...and start debugging...Hope this helps

 

[agump]

When you insert a ICON instance and one or more ILA instances into you logic , It changes into a part of your design. After you P&R your design and generate the bit file , you can download the bit file to the FPGA with any possible method. After this , your FPGA will be working as normal. Of course, the ICON and ILA instance are woking too. Now , you can run the Chipscope analyzer , it can communicate with the ICON instance in the FPGA with JTAG cable. When you run 'run' command in the Chipscope analyzer, it wil send the corresponding data to the ICON instance in the FPGA , When the ICON get the instruction , it will control the ILA as the instruction . After the ILS has got the required data, it will send them back to the Chipscope analyzer in the PC through the JTAG cable. This is how the Chipscope work.

 

[s3034585]

Hi All
Thanks for your replies...

Jayant this board has a jtag port also.

agump This means that i software can interact normaly with the fpga using pci port and at the same time i can debug using ILA thru jtap port. Am i right.....

so i can place ILA at any level of the hirearchy for which i need to monitor the values. What is a triger concept in it then.... I am unable to understand this..

thanks all of you...

 

[jayanth03]

Yeah u can place the ILA at the hierarchy you want...and the trigger is used to capture the events that happen once there is an event on the trigger input you have selected... there are some signals that you can't view with the ChipScope analyser...but these are shown as errors at compile time..so u don't have to worry...

Choose such an input as trigger such that after an event on this signal....you want the event on the required signals to be captured... hope this helps...

All you need to do is play around a little with ChipScope analyser.....

 

[agump]

Yes , you got it.
The triger is just some events . which decide when the ILA will begin to capture the signals. You define some expression or sequence of them. Then when the ILA detect them trun , it will start to capture the signal until them fill the RAM.

 

[jetset]

hum if you know the signals you should get, have a scope, and have available ports in your FPGA, you can route that signals to the free ports and manually meassure.

 

[s3034585]

Hi Guys
Thanks a lot for your comments and tips.. I tried to run chipscope as you guys had mentioned and it is working. Thanks a lot.
I have one dought. Chipscope uses unused block ram from fpga. Now when i load my design after power on reset. I get proper result which i expect as per the simulations. But after that if i try to trigger it again i see different results all together. Is it because i need to reset the FPGA again so that the block ram gets reset. What can be the possible reason for this kind of behaviour.

Waiting for your replies.
Thanks in advance
tama

 

[samuraign]

above guys have discussed for Xilinx.

Can anybody give some suggestions for signal tap analyzer of Altera.

Anybody is working on this can give their experiences.

 

[bansalr]

U can use Logic analyser. But for this u need debug ports and signals to be assigned on these ports to be viewed. The external logic analyser is much better and flexible than chipscope.

Because chipscope can store the data depending upon the BRAMS available.
Also u need JTAG communication

Added after 2 minutes:

Signal TAP analyser is simlar to chipscope. The ByteBlaster Cable is needed. and u have to instantaite the blobk from altera.