How to deal with the high input voltage of LDO

[godcadence]

site:www.edaboard.com 3.3v 5v breakdown

5v to 3.3v/1.8V LDO, design with 5v tolerance 0.18um process. Due to the 5V
input voltage,
the voltage between the drain and gate of the power pmos transistor
may exceed 5v, it may cause the transistor to break down,
how should I deal with this situation? Could anybody please tell me?

Can the mos oxide in process of 5V tolerance sustain the gate drain or source voltage of 5v?

 

[paley]

site:www.edaboard.com 3.3v 5v mos

If Vgs<=3.6V, that's OK

 

[godcadence]

+hot nwell +voltage +tsmc

The Vgs may be 5v during startup, will the transistor break down?

 

[floatice]

Pmos transistor you choose must be 5v tolerance transistor.Thought the process is 0.18um, the 5v tolerance transistor can sustain the gate drain or source voltage of 5v.

 

[safwatonline]

i think if it is a transient thing then that is OK

 

[mark_nctu]

Is the process only has 1.8V desice ?

 

[tsai_chin_wei]

it maybe help you..

 

[paley]

increase three external component?

 

[ericliu]

If considering the stress of power spikes during operation, the only way is to chose the thick-gate pmos (the dual gate process).

 

[cater]

There are many 5v to 1.8v/3.3v IP, but I don't know
how to design.

 

[okguy]

There are many 5v to 1.8v/3.3v IP, but I don't know
how to design.

5v tolerant digital I/Os use floating Nwell. But, for LDO input, I don't know.
I have also seen that IP : LDO with 5Vinput for 1.8/3.3v process.

 

[arghpok]

Are you worried about only for the Pmos integrity ?

You should buck those 5V down to the desire Vout + V drop-out. If you can't do that I cannot understand why you want to use a 5V input since it is gonna be detrimental for your power consumption as well for your chip integrity.

Use a DC/DC and/or decrease the input voltage. It's the smartest thing to do.

 

[lijianheng]

.18um MOSFET cann't stand 5V voltage, and Vdsat is large. Try to use other device.

 

[okguy]

.18um MOSFET cann't stand 5V voltage, and Vdsat is large. Try to use other device.

The IP exist for sale. I have seen its datasheet. The tricks is somewhere to use PMOS with very hot Nwell. But, I have never seen any paper or presentation on that kind of design ... anyone has a paper about it :?:

 

[leo_o2]

The max Vgs and Vdg of pass transistor PMOS will be 5V (supply voltage). The min gate voltage is 0V. The source voltage is 5V (supply voltage). If on overshoot, the drain voltage will be 3.6V in your case. So it is surely safe for 5V TSMC devices.

Added after 9 minutes:

Sorry, it seems no 5V device for 0.18um TSMC process. However, I think the weak point is Vgs not Vdg. With well controlled, Vdg will be under 3.6V that is no problem for 3.3V devices. Usually these devices will have much higher breakdown voltage than its safe operating voltage. For Vgs, it is a problem. You can use source follower at pre-driving stage that will clamp the voltage about a Vgs above ground. To be more conservative, a mini-clamp as ESD design can be added to protect the gate of Pass transistor PMOS.