The max Vgs and Vdg of pass transistor PMOS will be 5V (supply voltage). The min gate voltage is 0V. The source voltage is 5V (supply voltage). If on overshoot, the drain voltage will be 3.6V in your case. So it is surely safe for 5V TSMC devices.
Added after 9 minutes:
Sorry, it seems no 5V device for 0.18um TSMC process. However, I think the weak point is Vgs not Vdg. With well controlled, Vdg will be under 3.6V that is no problem for 3.3V devices. Usually these devices will have much higher breakdown voltage than its safe operating voltage. For Vgs, it is a problem. You can use source follower at pre-driving stage that will clamp the voltage about a Vgs above ground. To be more conservative, a mini-clamp as ESD design can be added to protect the gate of Pass transistor PMOS.