nicolas_pellissier
Newbie level 4
Hello,
How to deal with high fanout nets in synthesis with DC?
What happen in term of timing on this HFN ?
If I tell the synthesis tool by saying a command called as "set_ideal_net <net>". this way the synthesis tool knows the specified net as a high fanout net and does not buffer them .
What happen in term of timing ?
BR
Nicolas
How to deal with high fanout nets in synthesis with DC?
Warning: Design '' contains 5 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
Net 'i_ahbram/n2858': 2110 load(s), 1 driver(s)
Net 'i_cortexm0ds_wrapper/u_CORTEXM0DS/u_logic/htrans_o[0]': 1666 load(s), 1 driver(s)
Net 'i_ve_reggen/APB/ambacom_amba3_apb_rtl_r2p0_0_inst/po_core_if_rst_n': 1206 load(s), 0 driver(s), 20 inout(s)
Net 'i_ARC_wrapper/i_DW_arc_4m_cpu_top/u_cpu/u_pd1_domain/u_core/u_pipe/u_execute/u_regfile_2r2w/n1438': 1024 load(s), 1 driver(s)
Net 'i_ARC_wrapper/i_DW_arc_4m_cpu_top/u_cpu/u_clock_ctrl/u_clkgate3/clk_in': 2007 load(s), 0 driver(s), 78 inout(s)
What happen in term of timing on this HFN ?
If I tell the synthesis tool by saying a command called as "set_ideal_net <net>". this way the synthesis tool knows the specified net as a high fanout net and does not buffer them .
What happen in term of timing ?
BR
Nicolas
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