how to deal with high fanout net?

[nicolas_pellissier]

Hello,

How to deal with high fanout nets in synthesis with DC?

Warning: Design '' contains 5 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
Net 'i_ahbram/n2858': 2110 load(s), 1 driver(s)
Net 'i_cortexm0ds_wrapper/u_CORTEXM0DS/u_logic/htrans_o[0]': 1666 load(s), 1 driver(s)
Net 'i_ve_reggen/APB/ambacom_amba3_apb_rtl_r2p0_0_inst/po_core_if_rst_n': 1206 load(s), 0 driver(s), 20 inout(s)
Net 'i_ARC_wrapper/i_DW_arc_4m_cpu_top/u_cpu/u_pd1_domain/u_core/u_pipe/u_execute/u_regfile_2r2w/n1438': 1024 load(s), 1 driver(s)
Net 'i_ARC_wrapper/i_DW_arc_4m_cpu_top/u_cpu/u_clock_ctrl/u_clkgate3/clk_in': 2007 load(s), 0 driver(s), 78 inout(s)

What happen in term of timing on this HFN ?

If I tell the synthesis tool by saying a command called as "set_ideal_net <net>". this way the synthesis tool knows the specified net as a high fanout net and does not buffer them .
What happen in term of timing ?


BR
Nicolas

 

[The Commando]

There is a section in Synopsys DC compiler manual about the max_fanout variable, I am not sure how to set it though ... I've tried "set max_fanout <value>" before and it didn't work well with me.

 

[ThisIsNotSam]

There is a section in Synopsys DC compiler manual about the max_fanout variable, I am not sure how to set it though ... I've tried "set max_fanout <value>" before and it didn't work well with me.

this is not the same thing. you are telling the synthesis how to deal with one cell that connects to many cells. max_fanout determines the number of "many cells". what the OP is referring to are nets that connect to lots of points in your design. clock and reset are the typical cases, but other bus-like nets might behave as so.

in my experience, synthesis cannot handle these too well. you can let it add buffers if it thinks they are necessary, and then get physical synthesis to remove all of them later with optimization.

 

[slutarius]

Hello,

How to deal with high fanout nets in synthesis with DC?

What happen in term of timing on this HFN ?

If I tell the synthesis tool by saying a command called as "set_ideal_net <net>". this way the synthesis tool knows the specified net as a high fanout net and does not buffer them .
What happen in term of timing ?


BR
Nicolas

This can lead to very bad timing results because big delay of cells which drive the HFN.
This cause longer runtime and not good optimization in general.
Most of tools ussually focus on the worst timing path optimization, that why they make less on the others portions.

For synthesis, you can tell the tool to ignore this HFN by set_ideal_net command to make sure the rest regions are optimized also.
Later, in layout (Back-End), HFN can be solved by adding buffers and additional optimization.