Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to create a synchronous memory write enable without delays and negative edge flop

Status
Not open for further replies.
R

rakko

Full Member level 4
Joined
Jun 1, 2001
Messages
233
Helped
10
Reputation
20
Reaction score
6
Trophy points
1,298
Location
mozambic
Activity points
2,065
how can I create a synchronous memory write enable without delays and no negative edge flops? the write enable has to be at least 1/2 nanao second away from clock edges.

clock __|----|___|----|___|-----
wr_en___|----|_____
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top