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How to convert Xilinx verilog to Synopsys

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mohdfaisal

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How to convert Xilinx verilog source code to Synopsys source code and the testbench.:?:
 

sbob

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Huh? A little more information on what you are trying to do would be helpful. Are you just trying to simulate with VCS? Do you mean you have verilog source code that uses Xilinx primitives and you want to synthesize with DC?

Please explain more.
 

mohdfaisal

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Yes you are right. I am trying to simulate with VCS and trying to synthesize with DC. Can you help me?
 

sbob

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Hmm, well you still haven't told me what you are trying to target. Are you trying to generate a Xilinx FPGA image file, or are you trying to target something else?

To simulate "Xilinx" code with VCS, use the following command line:

vcs -Mupdate -F srcfiles

where srcfiles is a file that has your verilog source files listed in it. An example srcfile:

your_testbench.v
../chip/your_source1.v
../chip/your_source2.v
c:/Xilinx_8.1/verilog/src/glbl.v
-y c:/xilinx/verilog/src/unisims

The 2nd to last line is required for the xilinx global reset function, and the last line is required so VCS finds all the xilinx primitives.

If you are trying to target something other than a xilinx device, you will need to code generic versions of all xilinx primitives that you are using in your design and use those for synthesis (i.e. iobuffers, blockrams, fifo16s, DCMs, etc.)

To find out what primitives are being used, delete the last line in srcfile and look at the error messages when you compile with VCS.
 

uestchuang

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Hmm, well you still haven't told me what you are trying to target. Are you trying to generate a Xilinx FPGA image file, or are you trying to target something else?

To simulate "Xilinx" code with VCS, use the following command line:

vcs -Mupdate -F srcfiles

where srcfiles is a file that has your verilog source files listed in it. An example srcfile:

your_testbench.v
../chip/your_source1.v
../chip/your_source2.v
c:/Xilinx_8.1/verilog/src/glbl.v
-y c:/xilinx/verilog/src/unisims

The 2nd to last line is required for the xilinx global reset function, and the last line is required so VCS finds all the xilinx primitives.

If you are trying to target something other than a xilinx device, you will need to code generic versions of all xilinx primitives that you are using in your design and use those for synthesis (i.e. iobuffers, blockrams, fifo16s, DCMs, etc.)

To find out what primitives are being used, delete the last line in srcfile and look at the error messages when you compile with VCS.

hi,I take a try like this:
vcs -Mupdate -F test12.v t.v e:/XILINX/ISE_DS/ISE/verilog/src/glbl.v -y e:/XILINX/ISE_DS/ISE/verilog/src/unisims

but,it reported "Source file e:/XILINX/ISE_DS/ISE/verilog/src/glbl.v" cannot be opened for reading."
note: the "e:/XILINX/ISE_DS/ISE/verilog/src/glbl.v" was located in windows
do you know the problem about this? i am a fisher.
 

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