How to control the compiling order in simulation tool?

[AlexWan]

vcs timescale

In my design, there are many blocks. But for timescale reason, I have to control the compiling order during simulation.

Could you tell me sim tool(such as VCS or NC) how to control the compiling order? Or how to re-order the compiling order by my means?

Thanks.

 

[cnspy]

vcs override timescale

I think there are two methods to handle this.

First I will use timescale in the compile command to override those in design files.

the other is using the file list to compile your design.

 

[aji_vlsi]

compiling order

In my design, there are many blocks. But for timescale reason, I have to control the compiling order during simulation.

Could you tell me sim tool(such as VCS or NC) how to control the compiling order? Or how to re-order the compiling order by my means?

Thanks.

Hi,
Simple - if it is only timescale issue, use

vcs -timescale=1ns/1ns

IIRC, ncelab has the same/similar option.

HTH
Ajeetha, CVC
www.noveldv.com

 

[AlexWan]

highest timescale vcs

I have tried those method. But when I changed the timescale of some verilog files, the result will be different. And I can get the log file. It shows the timescale of some other files to be changed.

I am confused this. Any one can use those methods in your projects and get the ideal results?

I have contacted with AEs of VCS and NC. But they can't sure the order, only give me some notes from UG. There are some mistakes in those UGs.

 

[kermit]

vcs timescale overwrite

I think you can use the same timescale in the full design, just modify the most little scale as the timescale for the full design.
I think the effect on other file with large timescale is only slow the simulation, it wont affect the simulation result!