I have tried those method. But when I changed the timescale of some verilog files, the result will be different. And I can get the log file. It shows the timescale of some other files to be changed.
I am confused this. Any one can use those methods in your projects and get the ideal results?
I have contacted with AEs of VCS and NC. But they can't sure the order, only give me some notes from UG. There are some mistakes in those UGs.
I think you can use the same timescale in the full design, just modify the most little scale as the timescale for the full design.
I think the effect on other file with large timescale is only slow the simulation, it wont affect the simulation result!