How to check the influence of supply voltage noise on phase noise?

[diego.fan]

Hi, all

I'm designing a differential ring oscillator. I want to simulate the influence of supply voltage noise on phase noise.
I use "Number of noise/freq pairs" in vdc to generate noise, as Figure shows. I compare the phase noise with noise (Number of noise =2) and without noise (Number of noise=0).

Figure shows the results. My question is: because this is a differential oscillator, The noise from VDD should be a common mode signal. I think phase noise should have no difference, as the differential type rejects the common mode noise. But why is phase noise still different? The red curve in Figure is phase noise without vdd noise and the blue one is the one with vdd noise.

Thanks!

 

[dick_freebird]

I have seen people produce what they called "differential"
ring oscillators which were in fact -not- differential, but
rather -complementary- (antiphase inverter pairs, the idea
being to make power currents not-steppy for other RF
reasons). Since your fill-form junk covers the circuit I can't
say whether this is or isn't the case.

Even a truly differential circuit has a finite PSRR and so
any supply (and ground) noise will have a finite influence.
But complementary inverters will be worse.

If your input threshold moves differently with VDD than
the average of the high and low output levels, or the
high-going, low-going slew rates, then this is a way
that supply noise can enter the signal chain. You can
get phase noise, you can get duty cycle asymmetry
/ phase overlap / phase gap, that kind of thing.

 

[diego.fan]

Hi, I don't know what's complementary . To be honest, this is the first time I heard this. Could you please explain it more? I use DCVSL structure, similar to this paper
https://www.semanticscholar.org/pap...ingh/29a671100eb7a4d54031f55c5b5d8eaed50b6052

What's the meaning of "If your input threshold moves differently with VDD than the average of the high and low output levels, or the high-going, low-going slew rates"? What's input threshold? You mean the Vth of input transistors? The Vth won't change I think. From simulation result , nearly nothing can let Vth change. However In theory, voltage can change Vth a little. But I don't think this is a problem as voltage changes in all kinds of differential circuits. Its influence on Vth can be neglected.

 

[pancho_hideboo]

I don't know what's complementary .

I think it is a pseudo differential.

Even if your circuit is a true differential structure, CMRR is finite value.

 

[pancho_hideboo]

I think it is a pseudo differential.
Even if your circuit is a true differential structure, CMRR is finite value.

Forget this.

Show me netlist fragments regarding analysis statements.
And show me OCEAN script fragments regarding plot.

Noises of Out_p and Out_m are correlated like followings.

For contribution from even order sidebands, correlated as in phase.

For contribution from off order sidebands, correlated as 180deg phase difference.