How to check if the address bus mismatch

[akshayp]

Hi,

If i have one situation where my Address bus A[0:15], A[14] and A[13] are interchanged in the address mapping. how can i verify this bug.

Due to this mismatch complete Address mapping will change but as read and write on the given address will be fine. and will not give any error on any read/write.

Regards
Akshay

 

[vipinlal]

Can you be more clear about your question?Why do you want to "verify a bug"??

--vipin
https://vhdlguru.blogspot.com/

 

[imbichie]

By using "signal_force" command you can verify it na, its very easy i think

 

[akshayp]

consider a memory map which has address A[0:15]
and data bus as D[0:7];

and during mapping A[3] and A[4] are interchanged inside DUT so complete address range will be different.

write at Add = 0008h, the write will actually will happened on address 0004h consider that data is D

during read cycle Add = 0008h the read will actually happened on again on 0004h, and o/p will be D as expected so no issues . but address is wrongly checked. how we can check validity of address if it is mapped correctly to memory address.

hope this is fine

 

[vipinlal]

If you have completed writing the code and need to check it is working or not then you can use a testbench code. use a for loop in VHDL to write a value of "a" to the address "a". Once the data is written into the memory read it from the memory and see if it is same data written.

Use something like this in the testbench code.

for i in 0 to MemSize loop
addr <= i;
D <= i;
wait for clk_period;
ASSERT i = Dout_memory   
      REPORT "address translation is wrong" 
end loop;

The code may have syntax mistake.

--vipin

https://vhdlguru.blogspot.com/

 

[imbichie]

can you post your code with testbench here, then its easy to clear the problem