How to call a verilog module from another source

[kvinod423]

Hi I am new to Verilog coding.

I have created a module in one source file and wants to call the created module in a new other source file.

source 1 - contains full adder module
want to use full adder module created in source 1 file in source 2.

How can i do that ?

Thanks in advance.

 

[deepsetan]

Hi I am new to Verilog coding.

I have created a module in one source file and wants to call the created module in a new other source file.

source 1 - contains full adder module
want to use full adder module created in source 1 file in source 2.

How can i do that ?

Thanks in advance.

Hi,

What software did you use? Basically you just can instatiate your new module (full adder) as top module.

 

[sharath666]

There is no concept of "calling modules". You can instantiate the full adder module in source2 and access the ports of the full adder module in source2.