kvinod423
Newbie level 3

Hi I am new to Verilog coding.
I have created a module in one source file and wants to call the created module in a new other source file.
source 1 - contains full adder module
want to use full adder module created in source 1 file in source 2.
How can i do that ?
Thanks in advance.
I have created a module in one source file and wants to call the created module in a new other source file.
source 1 - contains full adder module
want to use full adder module created in source 1 file in source 2.
How can i do that ?
Thanks in advance.