Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to call a verilog module from another source

Status
Not open for further replies.

kvinod423

Newbie level 3
Joined
Apr 17, 2015
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
26
Hi I am new to Verilog coding.

I have created a module in one source file and wants to call the created module in a new other source file.

source 1 - contains full adder module
want to use full adder module created in source 1 file in source 2.

How can i do that ?

Thanks in advance.
 

deepsetan

Advanced Member level 4
Joined
May 8, 2013
Messages
119
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,298
Location
Malaysia
Activity points
2,137
Hi I am new to Verilog coding.

I have created a module in one source file and wants to call the created module in a new other source file.

source 1 - contains full adder module
want to use full adder module created in source 1 file in source 2.

How can i do that ?

Thanks in advance.

Hi,

What software did you use? Basically you just can instatiate your new module (full adder) as top module.
 

sharath666

Advanced Member level 2
Joined
Apr 4, 2011
Messages
552
Helped
126
Reputation
252
Reaction score
124
Trophy points
1,323
Location
India
Activity points
3,830
There is no concept of "calling modules". You can instantiate the full adder module in source2 and access the ports of the full adder module in source2.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top