How to calculate total number GND and PWR pin?

[Bajaj]

Hi All,

I have couple of questions.

1> How to calculate total number of GND and PWR pins required for ASIC?
It is percentage of total number of signal pins?
2> How to distribute GND and PWR pins for BGA packege?


TIA

 

[Manjunatha_hv]

There are good tools available from
OEA International
PPLAN
A VLSI power distribution network floor- planning tool used with P-GRID for optimizing the geometric configuration of VDD and VSS rings, internal power rails, and ring voltage source pad locations using estimated block current sources.
**broken link removed**
Ring Designer
**broken link removed**

and
Optimal Corporation
**broken link removed**


---manju---

 

[sunjimmy]

Hi,

For internal core logic, one PWR/GND pin-pair can sustain 100mA roughly. If you can use double or triple bonding, that will be better to reduce bonding wire inductance with lower switching noise on internal PWR/GND bus.
In terms of ESD, it's better to share one PWR/GND pin-pair for I/O rail per 12~16 Pads roughly for pad limited design.

hope it helps

 

[rakko]

The way I usually do this is to get the total power reported by the synthsis tool, look at the technology vendor datasheet for how much current a given wire size can handle per length. From these two I figure out how many power straps I need and draw a power mesh with a 10% extra margin. After layout I ran Astro-Rail to get a more accurate estimate and will adjust the mesh. At this point I know how much power the design needs. I then look at the power cells datasheet from the library vendor and find out how much power each of the IO power cells can supply. From here it's simple calculations. Once I finish this part, I re-run Astro-Rail on the whole chip and re-adjust if needed.

 

[funster]

1) How many GND and PWR pins do you need is up to the input and outputs pins

number and driving strength as well as ground bounce and power drop. this is

different for different condition.

2) you can distribute GND and PWR between signals evenly.


best regards

Hi All,

I have couple of questions.

1> How to calculate total number of GND and PWR pins required for ASIC?
It is percentage of total number of signal pins?
2> How to distribute GND and PWR pins for BGA packege?


TIA