can someone explain with example. ELAB-294: floating pin connected to ground,?

[narendra.04]

ELAB-294 Warning from design compiler tool, can someone explain with example. ELAB-294: floating pin connected to ground,?
cant we treat "Z" as floating here?

 

[Qwerty112233]

Seems like unconnected pin is hooked up to VSS by the tool? Can you check the elaborated netlist? do you have post synthesis netlist you can inspect this in?

 

[dick_freebird]

Is there perhaps a rule about "what to do with unconnected pins"?

Why do you have unconnected (or floating) pins?

 

[narendra.04]

Is there perhaps a rule about "what to do with unconnected pins"?

Why do you have unconnected (or floating) pins?

My intention is to understand ELAB-294 issue, which says, when previously unconnected pin has been connected to ground & check whether the behavior resulting from connected the pin to ground conforms to your expectation.

my understanding: design has a floating pin, after optimization the pin will be connected to ground

when i drive "z" after optimization tool is using tri-state cell,
so, what syntax or functional mistake i should make, in order to get warning(ELAB-294, floating pin connected to ground)

Thank you

 

[narendra.04]

Seems like unconnected pin is hooked up to VSS by the tool? Can you check the elaborated netlist? do you have post synthesis netlist you can inspect this in?

ok thanks,
ELAB-294 - when previously unconnected pin has been connected to ground & check whether the behavior resulting from connected the pin to ground conforms to your expectation.

what does it mean previously unconnected here?

i am trying to understand error message.

 

[Qwerty112233]

ok thanks,
ELAB-294 - when previously unconnected pin has been connected to ground & check whether the behavior resulting from connected the pin to ground conforms to your expectation.

what does it mean previously unconnected here?

i am trying to understand error message.

Sounds like rtl didn't have anything connected to that pin. But PNR tools don't want to leave floating gates. You'll see tie offs in synth, maybe even logic cones get optimized out..

So check the rtl if you can for that module.