How to calculate the Number of VDD/VSS pads required

[Prasanna Kumar]

pad sso

How can I use more accurate analysis or steps to determine the number of VDD/VSS (Power/Ground) Pads I should have in CHIP to supply enough current
and power for CHIP core and I/O pad.

There are two kind of Power Pad generally.
(1) VDD/VSS for core.
(2) VDD/VSS for I/O.
How to decide the number of them.

Thanks in Advance

Prasanna

 

[tarkyss]

significant determine vss

according with the current the vdd/vss provide and the current needed

 

[funster]

number of power and ground pad -patent

generally for inputs, you can use less VDD/VSS pair,

for outputs, you should use more VDD/VSS pairs.

because output pad consume much more current than input pad.

detailed decision is determined by your circuit's speed and capacitance load.

in another words, you must keep all signals clean and integrity.



best regards

How can I use more accurate analysis or steps to determine the number of VDD/VSS (Power/Ground) Pads I should have in CHIP to supply enough current
and power for CHIP core and I/O pad.

There are two kind of Power Pad generally.
(1) VDD/VSS for core.
(2) VDD/VSS for I/O.
How to decide the number of them.

Thanks in Advance

Prasanna

 

[lightcloud]

vdd current per gate

hi,
I think you should according to datasheet of the I/O pads,compute the amount
of the I/O pads.

 

[xysafety]

calculate speed from vss output

I agree viewpoint of fuster.
But i add my view: EMC rules must be considered.

 

[daisy]

vdd power pad

If you are using an ASIC library normally you will find formulas in the databook how to calculate the needed power pads. For instance:

VDD/VSS(i) [core power]
The number of VDD/VSS pad pairs = |0.001 x (0.0247 x S + 0.0047) x G x F / Iem| round-up
0.001 is order control factor (uA -> mA)
0.0247 is Average Switching Current per Gate (uA/MHz)
0.0047 is Average Hidden Current per Gate (uA/MHz)
S is the estimated switching activity (typically 0.1 for internal logic and 0.5 for I/O)
G is total gate count of the design
F is the operating frequency in MHz
Iem is the current limit per VDD/VSS pad pairs based on electromigration rule (40mA)

More formulas for the IO power pads are available.
Sometimes the IO pads are divided into pre-driver and output-driver.
Also always you have to consider electromigration and SSO (Simultaneous Switching Output). Basically the pads are split to SSO and NonSSO.
For the SSO pads the bigger number of VDD/VSS pairs of electromigration and noise have to be chosen then.
The total VDD/VSS pairs is then that plus the NonSSO VDD/VSS pairs considering electromigration.


For Foundry/COT libraries you will find also information in the databook for the library but not so nice formulas.
Actually only info for noise (SSO) and wire width (electromigration) is given.
The rest you should know for instance from an ASIC library databook.

Hope this helps to confuse

 

[Yun Lin]

1-vdd pad

I think three facts constrain the number of power pads.
1. DC power consumption.
2. SSO that may cause niose.
3. ESD consider.

 

[mopansen]

how to calculate vss

Can use Power Compiler to preestimate?

 

[suituse]

number of power/ground pad

But I am doubt Power compiler can just consiider the total current, but pay no attention to the esd and oss.