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step two: firmly grasp illusion that gate count is a useful metric on modern fpga's
step three: toss illusion out the window,. Weeeey! ^_^
step four: close window
Or the alternative version: whose "equivalent gate count" method would you like to use? And what do you think you can do with it?
Anyways: resource usage in terms of slices / clock resources / etc is a whole lot more useful on fpga IMO. And luckily you already get these in the synthesis report.
Q: i want to compare two area of design ,which way can i compare?
A: Resource usage in terms of slices / clock resources / etc is a whole lot more useful on fpga imo. And luckily you already get these in the synthesis report.
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