How to build buffer tree for RESET in SOC Encounter?

[david_zheng]

Dear all,

I want to build buffer tree for signal RESET like other clock nets,as so many max_tran vios occurred on this net under bc condition.
I add clock constrainst (skew,latency...) into clock spec file and then do CTS,tool reports that,clock net RESET does not have syn pin,and can not trace clock net RESET,my questions are:
1,how to define the RB pin of ff regestor driven by RESET as syn pin?
2,why only in bc condition, RESET have larger number of max_tran vios,while in wc condition,zero vios occur?

 

[rca]

you just need to create& modify by ahand a new ctstch file constraint, which will define the nreset source. Then you execute "clockDesign -specfile nreset.ctstch" to made the tree on this nets.

 

[david_zheng]

you just need to create& modify by ahand a new ctstch file constraint, which will define the nreset source. Then you execute "clockDesign -specfile nreset.ctstch" to made the tree on this nets.

yes,I created new ctstch file for RESET net,and perform "clockDesign -specfile ...",but CTS failed due to tool don't treat RB pin of FF as syn pin.
so I want to know how to define these RB pin that connect to RESET as syn pin, or if there is other method to hand hign fanout net like RESET?
thanks!

 

[vijji.sami]

yes,I created new ctstch file for RESET net,and perform "clockDesign -specfile ...",but CTS failed due to tool don't treat RB pin of FF as syn pin.
so I want to know how to define these RB pin that connect to RESET as syn pin, or if there is other method to hand hign fanout net like RESET?
thanks!

By default ,CTS treats set/reset pin of a flop as async r excluded pin.so it does not do clock tracing n skew analysis for Reset pin of flops.but u can make it as a sync pin .
I really dont think u hav gone through the SocUG(soc UserGuide manual) which can feed u with more information on how to do CTS than any thing. command reference manual,go through tis one also.so finally i dont want to disclose the statement that we hav to keep in specfile.just go through the manuals then u wil come to know.

So dont Scold me my friend,it is just for ur sake only.because u need to explore the things yourself most of the time,before poking to others right.

If Still there is an issue Plz let me Know.