how to break timing loops?

I found there are two timing loops after synthesis. As following:

Pin (timing loop #1)
--------------------------------------------------
U5/ZN
crossbar/vc_req_dec/U9/A1
crossbar/vc_req_dec/U9/ZN
crossbar/vc_req_dec/U27/I
crossbar/vc_req_dec/U27/ZN
crossbar/vc_req_dec/U28/I
crossbar/vc_req_dec/U28/ZN
crossbar/m2dm0/U37/I
crossbar/m2dm0/U37/Z
crossbar/vc_mux/U25/A4
crossbar/vc_mux/U25/ZN
crossbar/vc_mux/U22/A1
crossbar/vc_mux/U22/ZN
U5/I
U5/ZN
--------------------------------------------------

Pin (timing loop #2)
--------------------------------------------------
crossbar/vc_req_dec/U30/ZN
crossbar/m2dm4/U37/I
crossbar/m2dm4/U37/Z
crossbar/vc_mux/U24/I
crossbar/vc_mux/U24/ZN
crossbar/vc_mux/U22/A2
crossbar/vc_mux/U22/ZN
U5/I
U5/ZN
crossbar/vc_req_dec/U4/A1
crossbar/vc_req_dec/U4/ZN
crossbar/vc_req_dec/U29/I
crossbar/vc_req_dec/U29/ZN
crossbar/vc_req_dec/U30/I
crossbar/vc_req_dec/U30/ZN
--------------------------------------------------

The cell in these loops are all combination logic cell , so it's difficult for me to find it in RTL code and change code.


Could someone give me some advise to break these loops?

you can add some delay for them!

It's solved. I track tese loops and add DFF to breake them.

Just in case you encounter another loop =)

What I do is do a report_timing -loop before compile (after elaborate and reading the constraints). The cells in the report are unmapped and their names are closer to the original RTL.

It's hard to trace in a mapped netlist specially if DC ungroups hierarchies =)