lakkampally
Newbie level 3
Hi ,
I have the following doubt , would anyone explain , please.
I want to compile all RTL files , testbench files and testcases files, and after compilation , i want to select particular testcase to run ,
how can i achieve this in verilog ?
I just to avoid compiling all RTL files,testbench files, for every testcase run.
With the help of simulator i can do , i mean i can compile all RTL files , testbench files and i can reuse these compiled libraries , but is there any other way ?
Thanks in advance.
I have the following doubt , would anyone explain , please.
I want to compile all RTL files , testbench files and testcases files, and after compilation , i want to select particular testcase to run ,
how can i achieve this in verilog ?
I just to avoid compiling all RTL files,testbench files, for every testcase run.
With the help of simulator i can do , i mean i can compile all RTL files , testbench files and i can reuse these compiled libraries , but is there any other way ?
Thanks in advance.