how to avoid compiling of design files(RTL) for every test case run in verilog

[lakkampally]

Hi ,
I have the following doubt , would anyone explain , please.

I want to compile all RTL files , testbench files and testcases files, and after compilation , i want to select particular testcase to run ,
how can i achieve this in verilog ?

I just to avoid compiling all RTL files,testbench files, for every testcase run.

With the help of simulator i can do , i mean i can compile all RTL files , testbench files and i can reuse these compiled libraries , but is there any other way ?
Thanks in advance.

 

[dave_59]

If you can use SystemVerilog, this is quite easy because testbenches are written using dynamically constructed classes and you can read command line switches to help you select which classes to construct. The object-oriented nature of classes makes it possible to switch one class for another at many different levels of the testbench without having to modify the entire testbench.

You can read command line switches from the command line as well in Verilog, but you will have to organize your testcase into a set of tasks, and then use lots of case statements to select which test to run.

As you said, depending on which simulator you are using, you can also compile and elaborate your DUT in a separate step, then just compile the testbench and testcase as needed.

 

[lakkampally]

Thanks dave