How to assure that metastability won't happen

[safwatonline]

I have a fast clock and a slower one ,i want to sync. them , so i thought of sampling the slow by the fast but i am worried about the Metastability , is there someway to assure that Metastability wont happen

 

[no_mad]

Metastability

Hi,

If you want to this method, you can use 2 flip flops to tolerate metastability.

This is most common way to tolerate metastability.

Hope it helps.

 

[safwatonline]

Metastability

well, i can somehow get that the second flop will be stable for some extent but i cannot get how this can help the first flop (i.e. the 1st flop still be metastable)

 

[deh_fuhrer]

Re: Metastability

you cannot remove metastability,you can just make the design metastability tolerant by using synchronization logic...(If the data is stable in second flop and metastable in first flop then you dont have to worry about, as your final data is stable)..Anyways can you tell me which synchronizer are you using ??

 

[111111]

Re: Metastability

U need not to worry about the first flip flop. It will become metastable intermittently. You should be concerned that the output of 2nd FF should not be metastable

 

[safwatonline]

Metastability

well,if the first flop gives a wrong output due to metastability then the second cannot do anything about it, and i might get a stream of ones or zeros which "i think" would be fatal (as the jitter spec on the clock is tough)
about the synchronizer ,i didn't try any yet do u have any recommendation?
regards,
safwat

Added after 4 minutes:

ok, may be i am not clear enough, the problem here is that the both signals are clocks not just simple data ,so i have an option of using DLL to sync. them but i was wondering if there is a simpler solutions

 

[111111]

Re: Metastability

If the first FF goes metastable, then the the 2nd FF will sample it in the next clock cycle. So the first FF has time duration of 1 clock cycle, to settle its metastability.
The duration of metastability depends on which time of signal transition it is sampled. By using 2 FF synchronizer we have reduced that transition duration (and not eliminated it).
It may be possible that the output of 1st FF is still metastable when the 2nd FF is sampling it. Here the probability is more that 2nd FF will sample data wrongly that the possibility that 2nd FF will be metastable. The output of 2nd FF becomes correct in the next clock cycle.
In short Synchronizer should have 2 objectives:
1) 2nd FF should not be metastable
2) The occurence of event that the 2nd FF output is wrong (because it has sampled 1st FF which is still metastable at the next clock cycle) should be minimized.

 

[deh_fuhrer]

Re: Metastability

you'll still have the option left to use three flip-flops as synchronizer(generally used for very high frequency aplication when 2 flop is also metastable)..

 

[ALUOp]

Re: Metastability

you'll still have the option left to use three flip-flops as synchronizer(generally used for very high frequency aplication when 2 flop is also metastable)..

Does three flops really help?
Suppose the frequency is very high (like you said), and it takes more than 1 cycle for the signal to settle, then the signal going into the 2nd flop will still be metastable.
As a result, the 2nd flop will also send out a metastable signal to 3rd flop, and just like the metastable signal that came out of the 1st flop, this 2nd metastable signal will take more than one cycle to settle, so the signal will still be metastable when it arrives at the 3rd flop.
So, adding a flop does not help, right?
What you need should be more time to settle (i.e. longer cycle time); putting another flop will just push the metastable signal a cycle forward.
Please correct me if I am wrong.

 

[deh_fuhrer]

Re: Metastability

you'll still have the option left to use three flip-flops as synchronizer(generally used for very high frequency aplication when 2 flop is also metastable)..

Does three flops really help?
Suppose the frequency is very high (like you said), and it takes more than 1 cycle for the signal to settle, then the signal going into the 2nd flop will still be metastable.
As a result, the 2nd flop will also send out a metastable signal to 3rd flop, and just like the metastable signal that came out of the 1st flop, this 2nd metastable signal will take more than one cycle to settle, so the signal will still be metastable when it arrives at the 3rd flop.
So, adding a flop does not help, right?
What you need should be more time to settle (i.e. longer cycle time); putting another flop will just push the metastable signal a cycle forward.
Please correct me if I am wrong.

which cycle time are you talking about?

Added after 3 minutes:
the control signal duration should be more than the time period of slow clock..

 

[bharat_in]

Re: Metastability

I have heard a lot about MTBF, when it comes to metastablity.
Can anyone please, explain what is it and how does it affect the metastablity?

 

[safwatonline]

Metastability

well,i "think" that the MTBF "Mean time between failure" is just a representation of how often the synchronizer becomes metastable as far as i could remember it was inversely proportional to both the data freq. and the clock freq. and it was directly prop. to the exponential of the metastability duration so if u want a good stable sync. u should increase the MTBF

 

[wsctechnik]

Re: Metastability

you'll still have the option left to use three flip-flops as synchronizer(generally used for very high frequency aplication when 2 flop is also metastable)..

Does three flops really help?
Suppose the frequency is very high (like you said), and it takes more than 1 cycle for the signal to settle, then the signal going into the 2nd flop will still be metastable.
As a result, the 2nd flop will also send out a metastable signal to 3rd flop, and just like the metastable signal that came out of the 1st flop, this 2nd metastable signal will take more than one cycle to settle, so the signal will still be metastable when it arrives at the 3rd flop.
So, adding a flop does not help, right?
What you need should be more time to settle (i.e. longer cycle time); putting another flop will just push the metastable signal a cycle forward.
Please correct me if I am wrong.

Hi,

in my opinion, every stage of flop reduces the risk of MS by the same magnitude, which in turn depends on the used IC technology.

A metastable signal which is clocked into a flop, has a big chance to be correct and stable after this stage, because even a metastable signal has only a very little chance to meet exactly the conditions for generating metastability again.

Wolfgang