how to apply multicycle path on data to data check

data-to-data check

How to apply multicycle path on a data to data check. i mean when the data to data check is checked it is checked it is checked as multicycle path (say multicycle of 2). But since the data pins are also constrained wrt to clock pins, the multicycle path set on the data to data check should not affect this clock to data check .

ur questions is not very clear and confusing. can you post ur timing path report here and explain what ur questions is ?

chanpreet said:

How to apply multicycle path on a data to data check. i mean when the data to data check is checked it is checked it is checked as multicycle path (say multicycle of 2). But since the data pins are also constrained wrt to clock pins, the multicycle path set on the data to data check should not affect this clock to data check .

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I mean that i have .lib for a memory in which there is data to data check between address bits[15:0] and a select bit, now since that data-to-data setup check is always checked as a zero-cycle path, and hold is checked one cycle back ..right ??

But im interesting in checking the hold in a same cycle ( ie zero -cycle ), i dont want to check the setup since it is insured in the RTL that it adress bits are stable before the select comes and only changes after the select signal switches. Hence im interesting in only checking the hold not the setup in the same cycle.

Therefore i need to either set multicyle path whenever the above check is performed or is there any other way around ??

But since the address and select bits are also constrained with respect to clock pin and i dont want change this check.

Hi

If both data and address bits are constrained with respect to the clock, should there be any need for data check between them as they will have a relation between them too.

Please can you put your requirement in Diagram ?