Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to apply multicycle path on data to data check

Status
Not open for further replies.

chanpreet

Newbie level 3
Joined
Nov 3, 2006
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,307
data-to-data check

How to apply multicycle path on a data to data check. i mean when the data to data check is checked it is checked it is checked as multicycle path (say multicycle of 2). But since the data pins are also constrained wrt to clock pins, the multicycle path set on the data to data check should not affect this clock to data check .
 

kbulusu

Full Member level 2
Joined
Apr 23, 2003
Messages
138
Helped
27
Reputation
54
Reaction score
21
Trophy points
1,298
Activity points
900
ur questions is not very clear and confusing. can you post ur timing path report here and explain what ur questions is ?
chanpreet said:
How to apply multicycle path on a data to data check. i mean when the data to data check is checked it is checked it is checked as multicycle path (say multicycle of 2). But since the data pins are also constrained wrt to clock pins, the multicycle path set on the data to data check should not affect this clock to data check .
 

chanpreet

Newbie level 3
Joined
Nov 3, 2006
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,307
I mean that i have .lib for a memory in which there is data to data check between address bits[15:0] and a select bit, now since that data-to-data setup check is always checked as a zero-cycle path, and hold is checked one cycle back ..right ??

But im interesting in checking the hold in a same cycle ( ie zero -cycle ), i dont want to check the setup since it is insured in the RTL that it adress bits are stable before the select comes and only changes after the select signal switches. Hence im interesting in only checking the hold not the setup in the same cycle.

Therefore i need to either set multicyle path whenever the above check is performed or is there any other way around ??

But since the address and select bits are also constrained with respect to clock pin and i dont want change this check.
 

grvkpr18

Junior Member level 1
Joined
May 1, 2010
Messages
15
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,283
Location
India
Activity points
1,345
Hi

If both data and address bits are constrained with respect to the clock, should there be any need for data check between them as they will have a relation between them too.
 

dftrtl

Banned
Joined
Feb 1, 2011
Messages
349
Helped
76
Reputation
152
Reaction score
73
Trophy points
1,308
Location
Bangalore
Activity points
0
Please can you put your requirement in Diagram ?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top