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How reflect clock skew on input delays?

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ivlsi

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Hi All,

Let's say we need to define input delays of BB#1 (see the picture below). The inputs are driven from the clock, which is skewed from BB#1 clock (see the picture).

skew.jpg

The question: "How the clock skew should be represented in the input/output delay definitions?"

Thank you!
 

ivlsi

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How the clock skew should be reflected in the input/output delays?
 

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