# How reflect clock skew on input delays?

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#### ivlsi

Hi All,

Let's say we need to define input delays of BB#1 (see the picture below). The inputs are driven from the clock, which is skewed from BB#1 clock (see the picture).

The question: "How the clock skew should be represented in the input/output delay definitions?"

Thank you!

#### andre_teprom

##### Super Moderator
Staff member
Why don´t you insert some amount of D-ff´s to give a proper delay on the clock applied to BB#1 block, so that oversize the expected lag due to the logic ?

This could help ( on few words, go straight to the last paragraph ) :