How reflect clock skew on input delays?

[ivlsi]

Hi All,

Let's say we need to define input delays of BB#1 (see the picture below). The inputs are driven from the clock, which is skewed from BB#1 clock (see the picture).



The question: "How the clock skew should be represented in the input/output delay definitions?"

Thank you!

 

[andre_luis]

Why don´t you insert some amount of D-ff´s to give a proper delay on the clock applied to BB#1 block, so that oversize the expected lag due to the logic ?

This could help ( on few words, go straight to the last paragraph ) :
https://www.edaboard.com/threads/43611/#post200089

 

[ivlsi]

How the clock skew should be reflected in the input/output delays?