how "modulo" been synthesized in hardware?

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eexuke

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designware foundation (dwf) library

Dear all,
If I describe modulo operation in verilog, such as "a <= b % c",how can the synthesis tool help me to turn this into hardware? I think it is pretty hard for implementation if c is not equal to the power of 2......

Many thanks in advance!
 

modulo implementation hardware

Most synthesis tools will complain exactly as you predicted, with an error message that says "second operand must be a power of two".
Next step is to read the vendor's libraries manual to see if they provide an optimized division module.
 

I think you can use division to build the modulo...

If you want to get a <= b%c,

You can use:

d := b/c
a <= a - d*c

You can try whether it can work.

Please note I never do it by myself.

Just propose.

Best Regards,
Tony Tao
 

Tony Tao,
UR solution asks for 1 integer divider , 1 multiplier and then a subtraction operation to be done in one clock . .. It will be extermely difficult to meet timing with such arrangement . The soultion is by bit manipulation using barel shifters but for that the operand has to be power of 2 ! ... this is more viable from timing closure point of view . UR comments ...
 

If I describe modulo operation in verilog, such as "a <= b % c", how can the synthesis tool help me to turn this into hardware?
Click to expand...

Most basic synthesis tools (Xilinx ISE, Design Compiler, etc.) will not automatically synthesize % or DIVIDE (/).

Synopsys sells an enhanced arithmetic library (DesignWare Foundation) for the Design_Compiler product. If you have the DW-Foundation (DWF) license, then you can directly synthesize "a = b % c" -- the DWF license will create a hardware implementation using combinational logic.

I think Cadence PKS/Buildgates also has similar capability, but I need to check.

If you don't have access to either of these tools, then you'll have to come up with your own implementation.
 

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