how metastability does not occur in Async Fifo

[pintuinvlsi]

metastability fifo

Hi,

I have been asked a question in an interview. The question is:
If data is crossing from one clock domain to another clock domain then metastability condition occurs. Some time we use async fifo to avoid this. Then why metastability does not arise in async fifo? how can we transfer data from one domain to another without any problem?

Thanks

 

[vikas_lakhanpal27]

metastability clock domain

Async fifo supports 2 independent clock for data read and write(write happens on write clcok and read happens on read clcok) . So there is no chance of metstability.

 

[shobhitk]

sync flops

Basically there are Three Methods of Interfacing between Clock Domains :

1) Use Syncronizers ( Double Flopping , Mux-D ) etc
2) Asyncronious Fifo
3) Handshiking Mechanism ( With Syncronizers )

if you want to transfer one bit signal from one clock domain to other clock domain then Two or Three Stage Syncronizers are the Best Option

but if want to transfer more "piled up" signals means
releated signals such that Address, Data and Control then FIFO is good choice .

and One more method of of Handshaking based but to avoid metastability you have to use mutlibit syncronizers.

 

[easytarget]

async double sync flop

Can someone suggest a book that covers this subject and other similar dubjects? I don't think I'll find it in my digital logic design book.

 

[pintuinvlsi]

fifo and double flop sync

Thanks for all reply.
I have been asked some more questions about clock domain crossing which i could not answer satisfactory. Here are questions:

1. Why do we use 2 flops as synchronizer not more or less than that?

2. During metastabilty state after sync flop the output will get stable to 0 or 1. Then if we are sending logic 1 from one clock domain to another clock domain and after sync flop if it goes to logic 0 after metastablity, then how would we detect that or what should we do for that?

 

[XHL]

what is metastability in fifo

1. Why do we use 2 flops as synchronizer not more or less than that?

[Answer] - use more flops will reduce the possibility of metastability occur. You can use more
if you want.

2. During metastabilty state after sync flop the output will get stable to 0 or 1. Then if we are sending logic 1 from one clock domain to another clock domain and after sync flop if it goes to logic 0 after metastablity, then how would we detect that or what should we do for that?

[Answer] - if your source will stay at 1 for enough time (let's say more than 1 cycle of the destination clock domain), the output after sync flops will go high finally.

And use sync flops also means that you don't know exactly when the output go high - one cycle earlier or later.