How is the circuit under pad scheme realized?

[rajesh13]

How the circuit under pad scheme is realized.
Is there any potential problems associated with this scheme.

This is related to I/Os circuits in cmos process.

 

[sunking]

esd under pad

As normal, the circuit under pad is power tr. or startup circuit

 

[rfsystem]

circuit under pad

Active circuits under pad-metal are forbidden because of mechanical stress at bonding time. That lead to too much yield loss.

 

[yorande]

what is circuit under pad

How about ESD circuit under pad?

 

[rajesh13]

esd underpad

I think TI & Motorola are using this concept for years to save silicon area.

 

[sunking]

pad on circuit under pad

ESD can put under pad too,if it is a diode or bjt

 

[rajesh13]

active devices under bond pads

I am worried about about the things which "sfsystem" has mentioned. So what actually done to counter those stressfull bonding events.

 

[ptoo30]

circuits under bond pads

i do not suggest to use active area nor ESD circuit beneath pad. i only know the register was located beneath it on 2 um rule for LCD panel driver. but deep sub-micron process causes huge mechanical stress, even register will have gig fluctuation of characteristics.

 

[rajesh13]

control post16/ultrasonic/circuit

Do you have some information about the stress level which will be available to the circuit placed under pad.

 

[DoctorProf]

90nm wire bonding bond pad area

The process needs to be designed for ACTIVE AREA BONDING (AAB). This is the term used to describe puting circuitry under the bond pad. I work for a company that does this routinely in our internal processes. Many foundries do not allow this.

The mechanical stresses can be large but the failure typically is caused by mechnical fatigue of the oxide layers leading to cracks in the oxide under the pad. These cracks allow the various metal layers to short out.

The failures do not manifest themselves right away. Temperature cycling is the most effective way of stressing for this failure mechanism. We want our parts to pass electrically and not exhibit any cracks under the pad after 500 cycles from -65 to +150 C. If this occurs then we have a robust process.

I did a quick search on IEEE Xplore (https://ieeexplore.ieee.org/Xplore/DynWel.jsp) and found 85 articles on AAB (active <and> area <and> bonding).

 

[rajesh13]

pad on circuit bonding

So if I want to use this concept, I can use. Do I need to verify from the process people.

 

[DoctorProf]

circuit under pad layout

If the process allows it then there should be ground rules that determine how it can be used. I would check with the process guys or foundry to see if the process you are using allows AAB. If it does they should point you to the ground rules you need to follow to get reliable devices.

 

[sunking]

smic pad thickness

 

[rajesh13]

handbonded chips

If the process allows it then there should be ground rules that determine how it can be used. I would check with the process guys or foundry to see if the process you are using allows AAB. If it does they should point you to the ground rules you need to follow to get reliable devices.

I am using 90nm TSMC process.

 

[staric]

smic 0.18um low capacitance esd

There are many ESD device be designed under the pads I saw. I think it can save area. Most of these ESD device are diode ESD.

 

[Nobody]

circuit under pad <and> esd

as i know , there is one set of circuit under pad library from SMIC 0.18um . However no mass production data available for reference . So far it show sucessful under shuttle verification . Need for futher investigation about the reliability .

 

[sunking]

wire bonding aluminum pad with active circuitry

There are many kind of product has device under pad. such esd, startup circuit, body Res. and so on.
It is important that the device which is under pad is body device.

 

[jimjim2k]

over active area bondpad power mosfet

Hi


Look at this url for pad frames and more.

1. h**p://www.ece.iit.edu/~vlsi/cadence/pads/

A good tutorial on using cadence Tools (recommended)

2. h**p://www.ece.iit.edu/~vlsi/cadence/

* -> t

tnx

 

[andy2000a]

bonding over active circuit

I have one question .. I friend use umc 0.18um process
and put some CKT under PAD ..
then --> pad have pad_pilling problem .,,

 

[rajesh13]

bond pad tutorial cadence

I have one question .. I friend use umc 0.18um process
and put some CKT under PAD ..
then --> pad have pad_pilling problem .,,

Is this some kind of DRC problems. Like I have seen that few of the DRC tech. files have some rules that does no allow any active circuit to be placed under the PAD.