How is the circuit under pad scheme realized?

[Colbhaidh]

ciruit under pad

There can be process related issues to circuits beneath the bond pad. Typically in IC processing, there is a hyrogen anneal step to de-activate any "dangling bonds" in the cmos gate areas. Beneath the Bond Pad metal in modern technologies will be a Titanium Nitride and Titanium layer. This layer will stop hydrogen passing through. This would only really be an issue for circuits beneath the pad that need strick control over threshold voltage or where matching is a concern.
State of the art ultrasonic bonding should not be an issue with stress beneath the pads which is why TSMC and Chartered Semi allow some circuitry beneath the pads. I am surprised that UMC does not at 0.18um node.

 

[electronrancher]

circuit-under-pad

no no no! i disagree 100% with AAB

i saw horrible failures when some idiot tried to use AAB on his power mosfet. breakdown voltage was reduced by almost 80%, hot carrier wearout was much easier, all in all it was junk. the gates were crushed, the thin oxide (150A/0.6um process) was often cracked, the cross sections looked like hell!

i might put pn junctions under my bondpad, but NEVER gate or gateox. it might work for your experimental ceramic chips, using soft gold bondwire, hand bonded by someone who knows what they're doing... but in offshore production, bashing aluminum bondwires on at a rate of 10/second - your structures will be crushed, i promise you.

i know for a fact that carsem (actually a pretty good assembly house) could break the bondpads right out of any chip without barrier metal. even then the ILD thickness had to be increased to act as a shock absorber - and you want to put gateox under this? you should be wondering if your silicon itself is going to break!!

 

[rajesh13]

circuit under pad reliability test

no no no! i disagree 100% with AAB

i saw horrible failures when some idiot tried to use AAB on his power mosfet. breakdown voltage was reduced by almost 80%, hot carrier wearout was much easier, all in all it was junk. the gates were crushed, the thin oxide (150A/0.6um process) was often cracked, the cross sections looked like hell!

i might put pn junctions under my bondpad, but NEVER gate or gateox. it might work for your experimental ceramic chips, using soft gold bondwire, hand bonded by someone who knows what they're doing... but in offshore production, bashing aluminum bondwires on at a rate of 10/second - your structures will be crushed, i promise you.

i know for a fact that carsem (actually a pretty good assembly house) could break the bondpads right out of any chip without barrier metal. even then the ILD thickness had to be increased to act as a shock absorber - and you want to put gateox under this? you should be wondering if your silicon itself is going to break!!

If we use differrent type of dielectric / Mess sturcture of metal in PAD to relieve. Then it can be possible to use active device under PAD.

 

[electronrancher]

cadence circuit under pad

i don't think you need to use quote if our posts are right next to each other!

anyway, i was just offering my opinion - i know of several dielectrics that don't work, but none that do. if you have success, please post it here - i'd be interested to see your results.

 

[harveyg]

tsmc 90nm pad

I have never tried this but am considering it. Surely the key to success here is to treat it as a mechanical engineering problem. Likely its possible to create metal/via layouts which concentrate stress and others that equalize stress or perhaps still further ones that direct stress away from thin oxide.

So isn't it possible that for a carefully designed hand layout (like ESD) this might work without significant yield impact.

Meanwhile automatic place and route circuitry on the same process might not be successful because hidden in the jumble it creates is a stress concentrator over a fragile structure.

Any thoughts?

 

[electronrancher]

circuit under pad

the risk for diffused structures is low, but cmos i feel is a bad candidate for under-pad.

maybe probe pad if it's not going to be bonded. but these are few.

if anyone has cross-sections of a die with cmos gates under a pad that have survived, i would like to take a look at the ILD structre.

 

[harveyg]

Re: circuit under pad

What I am considering is a large area of thin oxide capacitance - so it could be made essentially featureless under the bond area.

I would be interested to know, did the the ILDs you have seen 'not work' fail around some under (or over) lying feature specifically?

(Intuitively even quite fragile materials can support considerable loads when sandwiched between tougher and conformal surfaces.)

Interested to know you thoughts.

 

[harveyg]

Re: circuit under pad

See paragraph 3 of article below


**broken link removed**

Kulicke & Soffa releases gold bonding wire technology

Silicon Strategies
09/13/2004, 10:05 AM ET

WILLOW GROVE, Pa. — Kulicke & Soffa Industries Inc. has released a new gold bonding wire technology for advanced wirebonding applications.

Called Radix, the wire has a higher intermetallic stability for improved reliability, according to the company. Radix bonding wire has shown superior reliability on a wide range of aluminum bond pad compositions and thicknesses, the company said.

The new bonding wire lowers hardness on free-air balls (FAB), which allows for bonding on sensitive devices structures like low-k dielectrics and bonding over active circuitry, it added.

"Many of our global customers have been asking for higher reliability without compromising lower electrical resistivity," said Ilan Hadar, K&S' vice president of bonding materials. "Radix wire gives customers the best of both worlds."

 

[Colbhaidh]

Re: circuit under pad

Typically for each layer of metal there is at least 0.8um of TEOS or similar oxide, and roughly 0.8 to 1um between Si at the 1st metal layer.
If you are using < 3 layers of metal, I would agree not to using circuitry under the pads. but for >3LM there will not be any significant stresses from the bonding at the transistor level. If there is, then there is a serious problem with the assembly site. I have been in IC processsing for > 20 years and never experienced assembly problems like that of CARSEM. (I have heard of problems with that particular company though ..).
Typical bonding pads are connected to underlying metal through a sea of tungsten plugs (sometimes, but not necessarily, directly beneath the bond - something I would not advise.) Tungsten is very hard compared to the oxide so if the ultrasonic weld moved the top layer metal sufficiently, it would crack the oxide between the plugs. This would be a severe reliability hazard and would fail the assembly house qualification if it existed.
I have seen active circuitry beneath tyhe pads on 5LM and 6LM at 0.18um and 0.13um with no issues (except matching mentioned above).

 

[Teddy]

Re: circuit under pad

I used circuit under pad before and will use it again.
Some foundries do not like it but you can surely have a waiver for that.
In our case it has to go through reliability testing and assembly site has to agree with that. In general technology guys do not have to care (especially when you use 3+ metal layers).
In old dayes they were putting N- / P- well under pad in case the wire would go "through" pad metal - but did not see it when 2+ metals arrived.
I would try it - with note to management that there could be some issues.
ESD? sure - active = "core" circuitry no thanks